Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III

In this paper, JPEG encoder application, one of the DSP applications, was implemented using the ASIP development system: PEAS-III. Instructions for JPEG encoder, such as DCT instruction, and butterfly instructions, were added to the initial design. Area, performance, and execution cycles of processors were calculated using generated HDL description, compiler, and assembler by PEAS-III. From experimental results, 12 architectures can be designed in 160 hours, and designer can select an optimal architecture that satisfies design constraints considering hardware cost, clock frequency and execution cycles.